Invention Grant
- Patent Title: Layout techniques for high-speed and low-power signal paths in integrated circuits with small channel devices
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Application No.: US15906116Application Date: 2018-02-27
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Publication No.: US10559532B2Publication Date: 2020-02-11
- Inventor: Marina Salik , Anirban Banerjee , Elizabeth Deleev Hylander-Priebe
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson & Sheridan, L.L.P
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/552 ; H01L21/8234 ; H01L23/66 ; H01L21/768 ; H01L27/02

Abstract:
Certain aspects of the present disclosure generally relate to layout techniques for high-speed and low-power signal paths in integrated circuits with small channel devices. More specifically, according to certain aspects, an integrated circuit may comprise a plurality of layers, wherein at least a portion of the plurality of layers is configured to form a power/ground grid having odd-numbered metal layers and even-numbered metal layers, wherein a majority of traces of the even-numbered metal layers have a first orientation, and wherein a majority of traces of at least one of the odd-numbered metal layers are oriented parallel to the majority of the traces of the even-numbered metal layers; and one or more circuit components configured to use high-speed, low-power signals carried by one or more of the plurality of layers and to be powered by the power/ground grid.
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Information query
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