Invention Grant
- Patent Title: Isolation enhancement with on-die slot-line on power/ground grid structure
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Application No.: US15875568Application Date: 2018-01-19
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Publication No.: US10559561B2Publication Date: 2020-02-11
- Inventor: Zhaoyin D. Wu , Parag Upadhyaya , Kun-Yung Chang
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Carleton Clauss
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/02 ; H01L21/76 ; H01L21/762 ; H01L21/768 ; H01L21/84 ; H01L23/522 ; H01L23/64

Abstract:
Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.
Public/Granted literature
- US20190229113A1 ISOLATION ENHANCEMENT WITH ON-DIE SLOT-LINE ON POWER/GROUND GRID STRUCTURE Public/Granted day:2019-07-25
Information query
IPC分类: