Invention Grant
- Patent Title: Semiconductor memory device
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Application No.: US15909432Application Date: 2018-03-01
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Publication No.: US10559586B2Publication Date: 2020-02-11
- Inventor: Taichi Iwasaki , Takeshi Sonehara , Hiroyuki Nitta
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JPP2017-126501 20170628
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11521 ; H01L27/11526 ; H01L27/11556 ; H01L27/11568 ; H01L27/11573 ; H01L23/00 ; H01L27/11565 ; H01L23/58 ; H01L21/78 ; H01L27/11519 ; H01L29/788 ; H01L29/792 ; H01L29/10 ; H01L21/02 ; H01L21/3205 ; H01L21/265 ; H01L21/3105 ; H01L21/311 ; H01L21/768 ; H01L21/321
Abstract:
A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first stacked body having a first, insulating, layer located on a surface of the substrate, a second, conductive, layer located over the first layer, and a third, insulating, layer located over the second layer, an opening extending through the first stacked body, a fourth, insulating, layer located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening, a fifth, insulating, layer, located over the fourth layer, and a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, wherein the composition of the third and fifth layers is different from that of the first and third layers.
Public/Granted literature
- US20190006384A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2019-01-03
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