Invention Grant
- Patent Title: Semiconductor device
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Application No.: US16063733Application Date: 2016-11-22
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Publication No.: US10559652B2Publication Date: 2020-02-11
- Inventor: Yutaka Fukui , Katsutoshi Sugawara , Shiro Hino , Kazuya Konishi , Kohei Adachi
- Applicant: Mitsubishi Electric Corporation
- Applicant Address: JP Chiyoda-ku
- Assignee: Mitsubishi Electric Corporation
- Current Assignee: Mitsubishi Electric Corporation
- Current Assignee Address: JP Chiyoda-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2016-022668 20160209
- International Application: PCT/JP2016/084570 WO 20161122
- International Announcement: WO2017/138215 WO 20170817
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/423 ; H01L29/417 ; H01L29/08 ; H01L29/36 ; H01L29/16 ; H01L29/78 ; H01L29/739 ; H01L29/10 ; H01L21/04 ; H01L21/02 ; H01L23/544 ; H01L29/66

Abstract:
A gate connection layer (14) includes a portion placed on an outer trench (TO) with a gate insulating film (7) being interposed. A first main electrode (10) includes a main contact (CS) electrically connected to a well region (4) and a first impurity region (5) within an active region (30), and an outer contact (CO) being spaced away from the active region (30) and in contact with a bottom face of the outer trench (TO). A trench-bottom field relaxing region (13) is provided in a drift layer (3). A trench-bottom high-concentration region (18) has an impurity concentration higher than that of the trench-bottom field relaxing region (13), is provided on the trench-bottom field relaxing region (13), and extends from a position where it faces the gate connection layer (14) with the gate insulating film (7) being interposed, to a position where it is in contact with the outer contact (CO) of the first main electrode (10).
Public/Granted literature
- US20190333986A1 SEMICONDUCTOR DEVICE Public/Granted day:2019-10-31
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