Invention Grant
- Patent Title: Nanosheet isolation for bulk CMOS non-planar devices
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Application No.: US15826375Application Date: 2017-11-29
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Publication No.: US10559654B2Publication Date: 2020-02-11
- Inventor: Balasubramanian Pranatharthiharan , Injo Ok , Soon-Cheon Seo , Charan Veera Venkata Satya Surisetty
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Steven J. Meyers
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78 ; H01L29/66 ; H01L29/16 ; H01L21/306 ; H01L29/775 ; H01L27/088 ; H01L21/8234 ; H01L29/423 ; B82Y10/00 ; H01L21/8238

Abstract:
A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench isolation structures surround the first and second device regions and extend below first and second pedestal portions of the semiconductor substrate. A first semiconductor material fin stack is located above the first pedestal portion of the semiconductor substrate, and a second semiconductor material fin stack is located above the second pedestal portion of the semiconductor substrate. Second trench isolation structures are located at ends of each first and second semiconductor material fin stacks. A portion of each second trench isolation structure is located directly between a bottommost surface of the first or second semiconductor material fin stack and the first or second pedestal portion of the semiconductor substrate.
Public/Granted literature
- US20180090566A1 NANOSHEET ISOLATION FOR BULK CMOS NON-PLANAR DEVICES Public/Granted day:2018-03-29
Information query
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