Invention Grant
- Patent Title: Vertical transport field-effect transistor including dual layer top spacer
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Application No.: US16252670Application Date: 2019-01-20
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Publication No.: US10559672B2Publication Date: 2020-02-11
- Inventor: Hemanth Jagannathan , Choonghyun Lee , Alexander Reznicek , Christopher Waskiewicz
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Otterstedt, Wallace & Kammer, LLP
- Agent L. Jeffrey Kelly
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/78 ; H01L21/28

Abstract:
A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a multi-layer top spacer that includes an oxygen barrier layer beneath a top dielectric layer. Techniques for fabricating the transistor include depositing the oxygen barrier layer over the gate stack prior to depositing the top dielectric layer. The oxygen barrier layer blocks oxygen diffusion during deposition of the top dielectric layer, thereby avoiding damage to underlying interfacial and gate dielectric layers.
Public/Granted literature
- US20190172924A1 VERTICAL TRANSPORT FIELD-EFFECT TRANSISTOR INCLUDING DUAL LAYER TOP SPACER Public/Granted day:2019-06-06
Information query
IPC分类: