Invention Grant
- Patent Title: Vertical FET with differential top spacer
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Application No.: US15960078Application Date: 2018-04-23
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Publication No.: US10559676B2Publication Date: 2020-02-11
- Inventor: Takashi Ando , Choonghyun Lee , Jingyun Zhang , Pouya Hashemi
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Vazken Alexanian
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/092 ; H01L29/78 ; H01L21/8238 ; H01L21/8234 ; H01L29/49

Abstract:
VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.
Public/Granted literature
- US20190326410A1 Vertical FET with Differential Top Spacer Public/Granted day:2019-10-24
Information query
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