Invention Grant
- Patent Title: Area-efficient single-legged SOI MOSFET structure immune to single-event-effects and bipolar latch-up
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Application No.: US15732138Application Date: 2017-09-25
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Publication No.: US10559693B2Publication Date: 2020-02-11
- Inventor: Ahmad Houssam Tarakji
- Applicant: Ahmad Houssam Tarakji
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L27/12 ; H01L29/45 ; H01L29/06
Abstract:
New device structure for single-legged Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI MOS) transistor is presented. This new structure imposes a hard barrier for an Impact-Ionizations current and for transients due to Single-Event-Effects (SEE's) in Body to laterally conduct (or diffuse) to the Source through the Body/Source junction. It forces these currents to conduct instead to the Source through an alternate path made of highly conductive Silicide. This alternate path effectively suppresses the latch-up of the built-in parasitic Bipolar structure without necessitating the incorporation of Body-Tied-Source (BTS) into the device layout which is known to increase the device periphery without correspondingly scaling its device current.
Public/Granted literature
- US20190097062A1 Area-Efficient Single-legged SOI MOSFET structure immune to single-event-effects and bipolar latch-up Public/Granted day:2019-03-28
Information query
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