A calibration circuit may comprise a negative pack terminal, an intermediate node, and a first protection IC coupled to a first transistor. The first transistor may be coupled between the negative pack terminal and the intermediate node. The calibration circuit may comprise a second protection IC coupled in parallel with the first protection IC and further coupled to a second transistor. A power source may be coupled in parallel with the first and second protection ICs, and a current source may be coupled between the negative pack terminal and the intermediate node, wherein the intermediate node is positioned between the first transistor and the second transistor, and the power source is configured to provide a current to the first protection IC through a first current loop.