A first PWM count computation unit computes a first PWM count for each of three phases in a first system. A second PWM count computation unit computes a second PWM count for each of three phases in a second system. Upper and lower switching elements for each phase in the first system are controlled in accordance with a first pattern in which the upper and lower switching elements are varied in the order of an upper on state, a lower on state, and the upper on state from the time of start of PWM cycles. Upper and lower switching elements for each phase in the second system are controlled in accordance with a second pattern in which the upper and lower switching elements are varied in the order of a lower on state, an upper on state, and the lower on state from the time of start of PWM cycles.