Invention Grant
- Patent Title: Probability-based optimization of system on chip (SOC) power
-
Application No.: US15854222Application Date: 2017-12-26
-
Publication No.: US10560116B2Publication Date: 2020-02-11
- Inventor: Nitin Kumar Chhabra , Rohit Halba , Shashi Kumar Shaw , Shrikrishna Nana Mehetre
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee Address: US CA Cupertino
- Agency: Westman, Champlin & Koehler, P.A.
- Main IPC: H03M11/00
- IPC: H03M11/00 ; H03M7/30 ; H04L25/02 ; G06F13/42 ; H04L27/06 ; H03M5/16 ; H03K19/0185 ; H04L25/49 ; H03K19/0175
Abstract:
A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.
Public/Granted literature
- US20190199371A1 PROBABILITY-BASED OPTIMIZATION OF SOC POWER Public/Granted day:2019-06-27
Information query
