A signal processing circuit includes: a processor configured to adjust phases of reception samples which is supplied at a supply interval, according to a phase adjustment amount; and a processing circuit including a finite impulse response (FIR) filter with taps and configured to process, by the FIR filter, each of the reception samples and output output symbols at an output interval different from the supply interval, the processor is configured to: derive initial values of tap coefficients for the respective taps; and derive the phase adjustment amount such that a center of centroids of the tap coefficients at respective output time points of the output symbols coincides with a center of a number of taps of the FIR filter, the tap coefficients at respective output time points of the output symbols being set according to a deviation between the supply interval and the output interval and the initial values.