A processor fetches instructions from a plurality of threads. Each entry in a branch information storage (BIS) stores a virtual address ID for a branch, information about the branch, and thread ID information. The BIS is accessed using a virtual address of an instruction to be fetched for a thread to determine whether a hit exists, and if so, to obtain the branch information stored in the entry that gave rise to the hit. The virtual address is converted into a physical address, and an address translation regime is specified for each thread. When allocating an entry into the BIS, allocation circuitry determines, for a branch instruction for a current thread, whether the address translation regime is shared by plural threads. If so, the allocation circuitry identifies both the current thread and any other thread for which the address translation regime is shared.