Invention Grant
- Patent Title: Ladder program analyzing device
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Application No.: US15598714Application Date: 2017-05-18
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Publication No.: US10565010B2Publication Date: 2020-02-18
- Inventor: Toshiyuki Matsuo , Mitsuru Mochizuki
- Applicant: FANUC CORPORATION
- Applicant Address: JP Yamanashi
- Assignee: FANUC CORPORATION
- Current Assignee: FANUC CORPORATION
- Current Assignee Address: JP Yamanashi
- Agency: Hauptman Ham, LLP
- Priority: JP2016-100578 20160519
- Main IPC: G06F9/48
- IPC: G06F9/48

Abstract:
A ladder program analyzing device that can present information for improving execution efficiency of a ladder program includes a ladder program analyzing unit and a ladder program analysis result displaying unit. The ladder program analyzing unit analyzes a ladder program including a plurality of ladder circuits and prepares an execution priority signal table in which execution priorities of the ladder circuits, reference signals indicating signals input to the ladder circuits, and update signals indicating signals output from the ladder circuits are correlated with each other. The ladder program analysis result displaying unit determines presence or absence of the ladder circuit improvable in execution efficiency by comparing the execution priorities, the reference signals, and the update signals of two of the ladder circuits on the basis of the execution priority signal table and displays the determination result.
Public/Granted literature
- US20170337082A1 LADDER PROGRAM ANALYZING DEVICE Public/Granted day:2017-11-23
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