Invention Grant
- Patent Title: Logic buffer for hitless single event upset handling
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Application No.: US15829542Application Date: 2017-12-01
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Publication No.: US10565048B2Publication Date: 2020-02-18
- Inventor: David Anthony Cananzi , Elliott B. Van Hartingsveldt , Michael Romain
- Applicant: Arista Networks, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Arista Networks, Inc.
- Current Assignee: Arista Networks, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Chamberlain, Hrdlicka, White, Williams & Aughtry
- Main IPC: G06F11/07
- IPC: G06F11/07 ; G11C7/10 ; G11C5/00 ; G06F11/18 ; G11C29/52

Abstract:
Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; asserting, based on detecting the state change, an initial state change device enable signal; transferring the first data from the first input to a first output of the initial state change device (which may be operatively connected to a second input of a state hold device); triggering, based on detecting the state change, a delay counter; making a determination that the delay period counted by the delay counter expired without receipt of an error detection signal; and based on the determination, asserting a state hold device enable signal to allow the data to pass from the second input to a second output of the state hold device.
Public/Granted literature
- US20190171508A1 LOGIC BUFFER FOR HITLESS SINGLE EVENT UPSET HANDLING Public/Granted day:2019-06-06
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