Invention Grant
- Patent Title: Hybrid logical to physical address translation for non-volatile storage devices with integrated compute module
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Application No.: US15726313Application Date: 2017-10-05
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Publication No.: US10565123B2Publication Date: 2020-02-18
- Inventor: Seung-Hwan Song , Arup De , Pankaj Mehra , Brian W. O'Krafka
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Main IPC: G06F12/1009
- IPC: G06F12/1009 ; G06F12/02

Abstract:
A host compiles code to perform a set of one or more database operations on target and embeds an indication of whether the target data is randomly accessed data or sequentially accessed data. The compiled code is transmitted to the compute engine inside a memory system that maintains a first portion of memory for storing sequentially accessed data and a second portion of memory for storing randomly accessed data. The memory system (e.g. SSD) maintains reduced size L2P tables in volatile working memory by maintaining coarse L2P tables in the working memory for use with sequentially accessed data and maintaining fine L2P tables in the working memory for use with randomly accessed data. The compute engine uses the compiled code to perform the set of one or more database operations on the target data using the working memory.
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Information query
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