An information processing apparatus includes processing circuitry. The processing circuitry processing circuitry is configured to acquire information sequentially in accordance with a first timeline; set, to the first timeline, a first timepoint and a second timepoint that is subsequent to the first timepoint on the first timeline; and present target information over a period between the second timepoint and a third timepoint that is subsequent to the second timepoint on the timeline, in accordance with a second timeline having a unit time shorter than a unit time of the first timeline. The target information is included in a period between the first timepoint and the third timepoint out of the acquired information.