Invention Grant
- Patent Title: Circuit configuration optimization apparatus and machine learning device
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Application No.: US15947835Application Date: 2018-04-08
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Publication No.: US10565343B2Publication Date: 2020-02-18
- Inventor: Hitoshi Izumi , Kenichiro Kurihara
- Applicant: FANUC Corporation
- Applicant Address: JP Yamanashi
- Assignee: FANUC CORPORATION
- Current Assignee: FANUC CORPORATION
- Current Assignee Address: JP Yamanashi
- Agency: Hauptman Ham, LLP
- Priority: JP2017-079851 20170413
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06N20/00 ; G06N3/02

Abstract:
A circuit configuration optimization apparatus includes a machine learning device that learns a circuit configuration of a FPGA device. The machine learning device observes circuit configuration data of the FPGA device and FPGA error occurrence state data indicating an error occurrence state of the FPGA device as state variables that express a current state of an environment. In addition, the machine learning device acquires determination data indicating propriety determination results of an operating state of the FPGA device. Then, the machine learning device learns the circuit configuration of the FPGA device in association with the FPGA error occurrence state data, using the state variables and the determination data.
Public/Granted literature
- US20180300442A1 CIRCUIT CONFIGURATION OPTIMIZATION APPARATUS AND MACHINE LEARNING DEVICE Public/Granted day:2018-10-18
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