Invention Grant
- Patent Title: Method and apparatus for load balancing in a ray tracing architecture
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Application No.: US15896013Application Date: 2018-02-13
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Publication No.: US10565775B2Publication Date: 2020-02-18
- Inventor: Tomas G. Akenine-Moller
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06T15/06
- IPC: G06T15/06 ; G06F8/41 ; G06F9/50 ; G06F9/38

Abstract:
An apparatus and method for load balancing in a ray tracing architecture. For example, one embodiment of a graphics processing apparatus comprises: an intersection unit engine to test a plurality of rays against a plurality of primitives to identify a closest primitive that each ray intersects; an intersection unit queue to store work to be performed by the intersection unit engine; and an intersection unit offload engine to monitor the intersection unit queue to determine a pressure level on the intersection unit engine, the intersection unit offload engine to responsively offload some of the work in the intersection unit queue to intersection program code executed on one or more execution units of the graphics processor.
Public/Granted literature
- US20180300941A1 METHOD AND APPARATUS FOR LOAD BALANCING IN A RAY TRACING ARCHITECTURE Public/Granted day:2018-10-18
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |
G06T15/06 | .光线跟踪 |