Invention Grant
- Patent Title: Semiconductor manufacturing methods for patterning line patterns to have reduced length variation
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Application No.: US16135669Application Date: 2018-09-19
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Publication No.: US10566207B2Publication Date: 2020-02-18
- Inventor: Gyeongseop Kim , Kyung Yub Jeon , Seul Gi Han
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Main IPC: H01L21/331
- IPC: H01L21/331 ; H01L21/308 ; H01L21/311 ; H01L21/033

Abstract:
A method for defining a length of a fin including forming a plurality of first slice walls on a mask material layer, which is provided over the fin, using a plurality of hard mask patterns, providing a plurality of fill mask patterns self-aligned with respect to the plurality of first slice walls to expose one or more select areas between one or more pairs of adjacent ones of the plurality of first slice walls, and providing a trim mask pattern including one or more openings and self-aligned with respect to the plurality of second slice walls to expose one or more of the plurality of first slice walls may be provided.
Public/Granted literature
- US20190198340A1 SEMICONDUCTOR MANUFACTURING METHODS FOR PATTERNING LINE PATTERNS TO HAVE REDUCED LENGTH VARIATION Public/Granted day:2019-06-27
Information query
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