A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.