Invention Grant
- Patent Title: Method of packaging power semiconductor module including power transistors
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Application No.: US15969897Application Date: 2018-05-03
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Publication No.: US10566258B2Publication Date: 2020-02-18
- Inventor: Kuniharu Muto , Koji Bando
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP2017-128640 20170630
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/495 ; H01L25/16 ; H01L25/00 ; H01L21/48 ; H01L23/40 ; H01L23/00 ; H01L25/07 ; H01L23/36 ; H01L25/18 ; H01L21/56 ; H01L23/29
Abstract:
Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.
Public/Granted literature
- US20190006258A1 METHOD OF MANUFACTURING SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE Public/Granted day:2019-01-03
Information query
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