Invention Grant
- Patent Title: Semiconductor logic device and system and method of embedded packaging of same
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Application No.: US15816360Application Date: 2017-11-17
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Publication No.: US10566301B2Publication Date: 2020-02-18
- Inventor: Raymond Albert Fillion , Kaustubh Ravindra Nagarkar
- Applicant: General Electric Company
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Ziolkowski Patent Solutions Group, SC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/528 ; H01L21/56 ; H01L25/00 ; H01L25/10 ; H01L25/065 ; H01L23/50 ; H01L23/31

Abstract:
A reconfigured semiconductor logic device includes a semiconductor logic device comprising a plurality of input/output (I/O) pads formed on an active surface thereof and a redistribution layer. The redistribution layer comprises an insulating layer formed atop the active surface of the semiconductor logic device such that the insulating layer does not extend beyond an outer perimeter of the active surface and a patterned conductive wiring layer positioned above the insulating layer. The patterned conductive wiring layer includes a plurality of terminal buses formed on a top surface of the insulating layer. Each terminal bus of the plurality of terminal buses is electrically coupled to multiple I/O pads of the plurality of I/O pads through vias formed in the insulating layer.
Public/Granted literature
- US20190157227A1 SEMICONDUCTOR LOGIC DEVICE AND SYSTEM AND METHOD OF EMBEDDED PACKAGING OF SAME Public/Granted day:2019-05-23
Information query
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