Invention Grant
- Patent Title: Method for forming gate structures for group III-V field effect transistors
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Application No.: US15882250Application Date: 2018-01-29
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Publication No.: US10566428B2Publication Date: 2020-02-18
- Inventor: Jeffrey R. LaRoche
- Applicant: Raytheon Company
- Applicant Address: US MA Waltham
- Assignee: Raytheon Company
- Current Assignee: Raytheon Company
- Current Assignee Address: US MA Waltham
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L29/40 ; H01L29/66 ; H01L21/285 ; H01L23/485 ; H01L29/417 ; H01L29/778 ; H01L21/28 ; H01L21/768 ; H01L21/8252 ; H01L23/48 ; H01L23/522 ; H01L23/532 ; H01L29/45 ; H01L29/47 ; H01L29/49 ; H01L29/20
Abstract:
A method for forming a gate structure for a Field Effect Transistor includes providing a semiconductor. A dielectric layer is formed over the semiconductor with an opening therein over a selected portion of the semiconductor. A deposition process is used to selectively deposit a gate metal over the dielectric layer and into the opening, the gate metal being deposited being non-adherent to the dielectric layer by the gate metal deposition process.
Public/Granted literature
- US20190237552A1 METHOD FOR FORMING GATE STRUCTURES FOR GROUP III-V FIELD EFFECT TRANSISTORS Public/Granted day:2019-08-01
Information query
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