Invention Grant
- Patent Title: Dual-operation depletion/enhancement mode high electron mobility transistor
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Application No.: US15958579Application Date: 2018-04-20
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Publication No.: US10566449B2Publication Date: 2020-02-18
- Inventor: John Bayruns , Robert J. Bayruns , Ashok T. Ramu
- Applicant: DUET MICROELECTRONICS LLC
- Applicant Address: US NJ Raritan
- Assignee: Duet Microelectronics, Inc.
- Current Assignee: Duet Microelectronics, Inc.
- Current Assignee Address: US NJ Raritan
- Agency: John H. Choi & Associates
- Main IPC: H01L31/072
- IPC: H01L31/072 ; H01L31/109 ; H01L29/778 ; H01L27/088 ; H01L29/10 ; H01L29/66

Abstract:
The present invention is a FET having a p-doped or acceptor-doped layer underneath a FET channel to enable E/D Mode operation. A FET threshold voltage is tunable through a voltage applied to the p-doped layer via a metal contact such as a threshold-control terminal (TCT). The present invention has a dual E/D mode operation of a single FET device, and also a dual E/D mode operation with a single-polarity positive power supply voltage. The FET of the present invention is fabricated to enable dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistors (HEMTs), to enable dual E/D Mode operation by incorporating a p-doped or acceptor doped region underneath the channel, to achieve a tunable threshold voltage by varying the bias voltage on a fourth terminal called the threshold-control terminal (TCT) that contacts the p-doped layer, and to enable Dual E/D-Mode operation of a HEMT with a single-polarity positive power supply voltage.
Public/Granted literature
- US20190326425A1 DUAL-OPERATION DEPLETION/ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR Public/Granted day:2019-10-24
Information query
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