Invention Grant
- Patent Title: Memory cell and memory device comprising selection device layer, middle electrode layer and variable resistance layer
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Application No.: US15862926Application Date: 2018-01-05
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Publication No.: US10566529B2Publication Date: 2020-02-18
- Inventor: Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2016-0020696 20160222
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
Public/Granted literature
- US20180145252A1 MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2018-05-24
Information query
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