Invention Grant
- Patent Title: Clock gating circuit
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Application No.: US16259631Application Date: 2019-01-28
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Publication No.: US10566977B2Publication Date: 2020-02-18
- Inventor: Ah-Reum Kim , Hyun Lee , Min-su Kim
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2015-0058762 20150427; KR10-2015-0139061 20151002
- Main IPC: H03K3/356
- IPC: H03K3/356 ; H03K19/0185 ; H03K19/00 ; H03K3/037 ; H03K3/012

Abstract:
Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.
Public/Granted literature
- US20190173472A1 CLOCK GATING CIRCUIT Public/Granted day:2019-06-06
Information query
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