Invention Grant
- Patent Title: Technologies for verifying a de-embedder for interconnect measurement
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Application No.: US15459248Application Date: 2017-03-15
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Publication No.: US10571501B2Publication Date: 2020-02-25
- Inventor: Xiaoning Ye , Kai Xiao
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G01R27/28
- IPC: G01R27/28

Abstract:
Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.
Public/Granted literature
- US20170269136A1 TECHNOLOGIES FOR VERIFYING A DE-EMBEDDER FOR INTERCONNECT MEASUREMENT Public/Granted day:2017-09-21
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