Invention Grant
- Patent Title: Lower-power semiconductor memory device
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Application No.: US16271947Application Date: 2019-02-11
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Publication No.: US10573376B2Publication Date: 2020-02-25
- Inventor: Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: SGPatents PLLC
- Priority: JP2001-324357 20011023
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G11C11/419 ; G11C5/14 ; G11C11/417 ; G11C11/412

Abstract:
A logic circuit in a system LSI (Large Scale Integrated Circuit) is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM (Static Random Access Memory) circuit of the system LSI controls a substrate bias to reduce leakage current.
Public/Granted literature
- US20190172528A1 SEMICONDUCTOR DEVICE Public/Granted day:2019-06-06
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