Microprocessor for gating a load operation based on entries of a prediction table
Abstract:
An apparatus for gating a load instruction is presented. The apparatus includes a memory to store a prediction table including an entry matching the load instruction. The matching entry includes a tag field to identify the load instruction, a distance field to indicate a distance of the load instruction to a prior aliasing store instruction, and a confidence field to indicate a prediction strength. The apparatus further includes a gating circuit operable to perform a look-up for the load instruction in the prediction table to find the matching entry and responsive to a determination of a valid prediction, retrieve a location of the prior aliasing store instruction using a value of the distance field of the matching entry, and perform a gating operation on the load instruction. The apparatus further includes a load store queue operable to provide feedback for updating the matching entry after the load instruction has executed.
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