Invention Grant
- Patent Title: Chip and power planning method
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Application No.: US16046684Application Date: 2018-07-26
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Publication No.: US10579765B2Publication Date: 2020-03-03
- Inventor: Jai-Ming Lin , Jhih-Sheng Syu , Bo-Yuan Huang
- Applicant: NCKU Research and Development Foundation , Himax Technologies Limited
- Applicant Address: TW Tainan TW Tainan
- Assignee: NCKU Research and Development Foundation,Himax Technologies Limited
- Current Assignee: NCKU Research and Development Foundation,Himax Technologies Limited
- Current Assignee Address: TW Tainan TW Tainan
- Agency: Stout, Uxa & Buyan, LLP
- Agent Donald E. Stout
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.
Public/Granted literature
- US20200034506A1 CHIP AND POWER PLANNING METHOD Public/Granted day:2020-01-30
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