An exemplary embodiment of present disclosure provides a display device including a first horizontal line, a first delay line, a second delay line, a delay value determiner, and a timing controller. The first horizontal line receives a gate pulse signal (CPV) generated by a gate driver. The first delay line is connected to the first horizontal line to transmit a gate pulse signal received at a first horizontal position as a first delay signal. The second delay line is connected to the first horizontal line to transmit a gate pulse signal received at a second horizontal position as a second delay signal. The delay value determiner generates a horizontal delay signal based on the first delay signal and the second delay signal. The timing controller determines generation times of line latch signals applied to a plurality of data lines based on the horizontal delay signal.