- Patent Title: Systems and methods for generating stagger delays in memory devices
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Application No.: US16593675Application Date: 2019-10-04
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Publication No.: US10580478B2Publication Date: 2020-03-03
- Inventor: Michael V. Ho
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: G11C11/16
- IPC: G11C11/16 ; G11C11/4076 ; G11C7/22 ; G11C11/4093 ; G06F13/16 ; G11C7/10

Abstract:
A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.
Public/Granted literature
- US20200035290A1 SYSTEMS AND METHODS FOR GENERATING STAGGER DELAYS IN MEMORY DEVICES Public/Granted day:2020-01-30
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