Invention Grant
- Patent Title: Semiconductor apparatus with multiple tiers, and methods
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Application No.: US15645635Application Date: 2017-07-10
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Publication No.: US10580790B2Publication Date: 2020-03-03
- Inventor: Toru Tanzawa
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L29/74
- IPC: H01L29/74 ; H01L27/11582 ; H01L27/11524 ; H01L27/11531 ; H01L27/11556 ; H01L27/1157 ; H01L27/11573 ; G11C8/10 ; H01L21/02 ; H01L27/11529 ; H01L29/49
Abstract:
Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.
Public/Granted literature
- US20170309641A1 SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS Public/Granted day:2017-10-26
Information query
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