Invention Grant
- Patent Title: Trench semiconductor device layout configurations
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Application No.: US15900571Application Date: 2018-02-20
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Publication No.: US10580861B2Publication Date: 2020-03-03
- Inventor: Dosi Dosev , Don Rankila , Tatsuya Kamimura , Shunsuke Fukunaga , Steven Kosier , Peter West
- Applicant: Polar Semiconductor, LLC , SANKEN ELECTRIC CO., LTD.
- Applicant Address: US MN Bloomington JP Saitama
- Assignee: POLAR SEMICONDUCTOR, LLC,SANKEN ELECTRIC CO., LTD.
- Current Assignee: POLAR SEMICONDUCTOR, LLC,SANKEN ELECTRIC CO., LTD.
- Current Assignee Address: US MN Bloomington JP Saitama
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/78

Abstract:
A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.
Public/Granted literature
- US20180175146A1 TRENCH SEMICONDUCTOR DEVICE LAYOUT CONFIGURATIONS Public/Granted day:2018-06-21
Information query
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