Embodiments of memory block erasure are described herein. An aspect includes determining a first word line set consisting of a first plurality of word lines. Another aspect includes activating the first plurality of word lines, such that a respective memory cell that is connected to each of the first plurality of word lines is erased by the activation of the first plurality of word lines. Another aspect includes determining a second word line set, wherein the second word line set consists of the first word line set and a second plurality of word lines. Another aspect includes simultaneously activating the first plurality of word lines and the second plurality of word lines, such that a respective memory cell that is connected to each of the second plurality of word lines is erased by the activation of the first plurality of word lines and the second plurality of word lines.