Invention Grant
- Patent Title: Fine-grained analog memory device based on charge-trapping in high-K gate dielectrics of transistors
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Application No.: US15595680Application Date: 2017-05-15
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Publication No.: US10585643B2Publication Date: 2020-03-10
- Inventor: Xuefeng Gu , Subramanian S. Iyer
- Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
- Applicant Address: US CA Oakland
- Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
- Current Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
- Current Assignee Address: US CA Oakland
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: G06N3/063
- IPC: G06N3/063 ; G11C11/54 ; G06F7/02 ; H01L29/792 ; G11C27/00 ; G11C16/04
Abstract:
A fine-grained analog memory device includes: 1) a charge-trapping transistor including a gate and a high-k gate dielectric; and 2) a pulse generator connected to the gate and configured to apply a positive or negative pulse to the gate to change an amount of charges trapped in the high-k gate dielectric.
Public/Granted literature
- US20170329575A1 FINE-GRAINED ANALOG MEMORY DEVICE BASED ON CHARGE-TRAPPING IN HIGH-K GATE DIELECTRICS OF TRANSISTORS Public/Granted day:2017-11-16
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