Invention Grant
- Patent Title: Reducing stalling in a simultaneous multithreading processor by inserting thread switches for instructions likely to stall
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Application No.: US16049929Application Date: 2018-07-31
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Publication No.: US10585669B2Publication Date: 2020-03-10
- Inventor: Takeshi Ogasawara
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Intellectual Property Law
- Agent Jon Gibbons
- Priority: JP2012-179345 20120813
- Main IPC: G06F8/41
- IPC: G06F8/41 ; G06F9/30 ; G06F9/38

Abstract:
A system and method suppresses occurrence of stalling caused by data dependency other than register dependency in an out-of-order processor. A stall reducing method includes a handler for detecting a stall occurring during execution of execution code using a performance monitoring unit, and for identifying, based on dependencies, a second instruction on which a first instruction is data dependent, the stall based on this dependency. A profiler registers the second instruction as profile information. An optimization module inserts a thread yield instruction in an appropriate position inside execution code or an original code file based on the profile information, and outputs optimized execution code.
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