A power supply diagnostic strategy for discrete power supply diagnostic states is independent of the underlying memory structure. The values used in the associated algorithm are selected to ensure that random linked failures will be detected. This applies to planar memory structures with 1, 2, 4, 6, 8, 12, and 16 common lattices, or physical memory structures with individual bit dispersed memories with 1, 2, 4, 6, 8, 12, and 16 consecutive bit splices. Further, the strategy provides that the various monitored voltage tables remains distinct even with compiler optimization activated.