Invention Grant
- Patent Title: Procedures for implementing source based routing within an interconnect fabric on a system on chip
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Application No.: US16369612Application Date: 2019-03-29
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Publication No.: US10585825B2Publication Date: 2020-03-10
- Inventor: Shailendra Desai , Robert Totte , Juan Sierra , Parimal Gaikwad , Amit Jain , Mark Pearce
- Applicant: Provino Technologies, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: PROVINO TECHNOLOGIES, INC.
- Current Assignee: PROVINO TECHNOLOGIES, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Beyer Law Group LLP
- Main IPC: G06F13/20
- IPC: G06F13/20 ; G06F9/46 ; G06F9/48 ; G06F13/362 ; G06F13/366 ; G06F9/54 ; G06F13/40 ; G06F15/78

Abstract:
Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
Public/Granted literature
- US20190303320A1 PROCEDURES FOR IMPROVING EFFICIENCY OF AN INTERCONNECT FABRIC ON A SYSTEM ON CHIP Public/Granted day:2019-10-03
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