- Patent Title: Method and system for verification using combined verification data
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Application No.: US15915365Application Date: 2018-03-08
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Publication No.: US10586014B1Publication Date: 2020-03-10
- Inventor: Yael Kinderman , David Spatafore , Nili Segal , Yan Yagudayev , Vincent Reynolds
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Pearl Cohen Zedek Latzer Baratz LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method for combining verification data may include using a processor, obtaining verification data and a verification model from each of a plurality of verification engines relating to different verification methods, the verification data relating to a plurality of verification tests that were conducted on a design under test (DUT) using the plurality of verification engines; using a processor, merging the verification models obtained from the plurality of verification engines into a merged verification model; using a processor, calculating a combined verification metric grade for a plurality of verification entities in the merged verification model using verification metric grades for each of the plurality of verification entities calculated from the verification data obtained from the plurality of engines and applying a combined verification metric grade rule; and outputting the combined verification metric grade via an output device.
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