Invention Grant
- Patent Title: Gate height and spacer uniformity
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Application No.: US15608476Application Date: 2017-05-30
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Publication No.: US10586741B2Publication Date: 2020-03-10
- Inventor: Kangguo Cheng , Lawrence A. Clevenger , Balasubramanian S. Pranatharthi Haran , John Zhang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Joseph Petrokaitis
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78 ; H01L29/66 ; H01L21/8234 ; H01L21/033 ; H01L21/311

Abstract:
Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate. A dielectric layer is formed on the substrate and above top surfaces of the first and second sacrificial gates. A self-aligned protection region is formed to cover a first portion of the dielectric layer and a second uncovered portion of the dielectric layer is removed. The first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.
Public/Granted literature
- US20180122710A1 GATE HEIGHT AND SPACER UNIFORMITY Public/Granted day:2018-05-03
Information query
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