Invention Grant
- Patent Title: 3D cross-point memory manufacturing process having limited lithography steps
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Application No.: US15628317Application Date: 2017-06-20
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Publication No.: US10586794B2Publication Date: 2020-03-10
- Inventor: Mac D. Apodaca , Daniel Robert Shepard
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Stoel Rives LLP
- Agent Joseph J. Hawkins
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L29/06 ; H01L23/528 ; H01L23/522 ; H01L23/532 ; H01L27/10 ; H01L49/02

Abstract:
The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers.
Public/Granted literature
- US20170287906A1 3D CROSS-POINT MEMORY MANUFACTURING PROCESS HAVING LIMITED LITHOGRAPHY STEPS Public/Granted day:2017-10-05
Information query
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