Invention Grant
- Patent Title: Multi-layer wiring structure, method for manufacturing multi-layer wiring structure, and semiconductor device
-
Application No.: US15890894Application Date: 2018-02-07
-
Publication No.: US10586804B2Publication Date: 2020-03-10
- Inventor: Takahiro Tomimatsu
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2017-181288 20170921
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L27/11582 ; H01L27/1157 ; H01L27/11565 ; H01L23/528 ; H01L21/768 ; H01L23/00 ; G11C16/04 ; H01L23/522 ; G11C16/06 ; H01L27/11573

Abstract:
According to one embodiment, a multi-layer wiring structure includes a first multi-layer section, first contact plugs, and pillars. First conductors and first insulators are alternately layered in the first multi-layer section. The multi-layer section includes a first area that includes memory cells, and a second area different from the first area. The first contact plugs are formed in the first holes extending from an uppermost layer of the first multi-layer section respectively to the first conductors in the second area, side surfaces of the first contact plugs being covered with first insulating films. The pillars are formed of second insulators and passing through the first multi-layer section in a layered direction in the second area.
Public/Granted literature
Information query
IPC分类: