DC-DC voltage reducing converter with a test mode operation
Abstract:
A voltage reducing circuit includes a power switch circuit portion having high-side and low-side field-effect-transistors connected at a switch node. The power switch circuit portion has an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled and, vice versa, an off-state. An energy storage circuit portion including an inductor connected to the switch node is arranged to provide an output voltage. A timer determines a falltime duration required for the output voltage to fall to a threshold value. A controller switches the voltage reducing circuit between a first mode of operation in which a periodic pulse width modulated drive signal is applied to the high-side and low-side field-effect-transistors; and a second mode of operation in which a pulse is applied to the high-side and low-side field-effect-transistors only if the output voltage reaches the threshold value.
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