Invention Grant
- Patent Title: Cache memory with reduced power consumption mode
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Application No.: US15607921Application Date: 2017-05-30
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Publication No.: US10591978B2Publication Date: 2020-03-17
- Inventor: Patrick P. Lai , Robert Allen Shearer
- Applicant: Microsoft Technology Licensing, LLC
- Applicant Address: US WA Redmond
- Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
- Current Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
- Current Assignee Address: US WA Redmond
- Agency: Alleman Hall Creasman & Tuttle LLP
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F1/3234 ; G06F12/0846 ; G06F1/3287

Abstract:
Processors may include cache circuitry that is a significant source of power consumption. A cache is going to be placed into a lower power mode. Based at least in part on this anticipated transition, the contents of the cache data lines are copied into persistent storage. While the cache is in the lower power mode, the tag circuitry is kept operational. When an access request is made to the cache, a relatively fast lookup of the tag in the tag array can be made. The location where the associated cache line is stored in the persistent storage may be determined from the tag data. Upon a tag hit, the system is able to find the contents of the requested cache line in the persistent storage without returning the storage array of the cache to a fully operational state.
Public/Granted literature
- US20180348847A1 CACHE MEMORY WITH REDUCED POWER CONSUMPTION MODE Public/Granted day:2018-12-06
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