A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m≥1, and k*m memories, where k≥2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories. Each sample collector is configured to calculate a respective memory select in dependence upon the address in each of the d dimensions such that each sample collector selects a different one of the k*m memories so as to allow the sample collectors to access k of the k*m memories concurrently. A memory controller may comprise m memory access units for handling transfers of samples in a d-dimensional array between m data buses and k*m memories. An integrated circuit (IC) comprising a memory access unit, and a motor vehicle comprising a computing device having a memory access unit are also disclosed.