Invention Grant
- Patent Title: Optimizing integrated circuit designs based on interactions between multiple integration design rules
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Application No.: US15816210Application Date: 2017-11-17
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Publication No.: US10592627B2Publication Date: 2020-03-17
- Inventor: Dureseti Chidambarrao , Jason D. Hibbeler , Dongbing Shao , Steven Zebertavage
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Michael A. Petrocelli
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L27/02

Abstract:
A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.
Public/Granted literature
- US20190095551A1 OPTIMIZING INTEGRATED CIRCUIT DESIGNS BASED ON INTERACTIONS BETWEEN MULTIPLE INTEGRATION DESIGN RULES Public/Granted day:2019-03-28
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