Invention Grant
- Patent Title: Information protection method and device based on a plurality of sub-areas for MCU chip
-
Application No.: US15505616Application Date: 2015-01-30
-
Publication No.: US10592644B2Publication Date: 2020-03-17
- Inventor: Baokui Li , Jinghua Wang , Nanfei Wang
- Applicant: GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
- Applicant Address: CN Beijing
- Assignee: GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
- Current Assignee: GIGADEVICE SEMICONDUCTOR (BEIJING) INC.
- Current Assignee Address: CN Beijing
- Agent Gokalp Bayramoglu
- Priority: CN201410850607 20141230
- International Application: PCT/CN2015/071983 WO 20150130
- International Announcement: WO2016/106933 WO 20160707
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F21/12 ; G06F12/14 ; G06F21/78 ; G06F13/42 ; G06F21/85 ; G06F21/53 ; G06F13/40

Abstract:
An information protection method and device based on a plurality of sub-areas for an MCU chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory, the method comprises: determining a preceding sub-area when the instruction bus accesses the user area; entering corresponding preceding sub-area working state; determining the current sub-area when the instruction bus accesses the user area; when the preceding sub-area is inconsistent with the current sub-area, entering the transition state; determining whether the duration of the transition state reaches the preset waiting time; if yes, entering the corresponding current sub-area working state. The information protection method and device prevent the cooperative companies which develop the program together from stealing program from each other.
Public/Granted literature
- US20170277871A1 INFORMATION PROTECTION METHOD AND DEVICE BASED ON A PLURALITY OF SUB-AREAS FOR MCU CHIP Public/Granted day:2017-09-28
Information query