A semiconductor memory device may include a memory cell array, a peripheral circuit and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a program operation on a selected memory block among the memory blocks. The control logic may control the program operation of the peripheral circuit. The selected memory block may be coupled with a plurality of bit lines, and the bit lines may be grouped into a first bit line group and a second bit line group based on programming speeds of memory cells coupled to the bit lines that are grouped into the first and second bit line groups. During a blind program operation of the selected memory block, the control logic may control the peripheral circuit to apply different program permission voltages to bit lines of at least two bit line groups.